Fully On-Chip MAC at 14 nm Enabled by Accurate Row-Wise Programming of PCM-Based Weights and Parallel Vector-Transport in Duration-Format

Hardware acceleration of deep learning using analog non-volatile memory (NVM) requires large arrays with high device yield, accuracy Multiply-ACcumulate (MAC) operations, and routing frameworks for implementing arbitrary neural network (DNN) topologies. In this article, we present a 14-nm test-chip Analog AI inference—it contains multiple phase change (PCM)-devices, each array capable storing 512 $\times $ unique DNN weights executing massively parallel MAC operations at the location data. excitations are transported across chip duration representation on reconfigurable 2-D mesh. To accurately transfer inference models to chip, describe closed-loop tuning (CLT) algorithm that programs four PCM conductances in weight, achieving <3% average weight-error. A row-wise programming scheme associated circuitry allow us execute CLT up concurrently. We show test can achieve near-software-equivalent two different DNNs. demonstrate tile-to-tile transport fully-on-chip two-layer MNIST (accuracy degradation ~0.6%) resilience error propagation long sequences (up 10 000 characters) recurrent short-term (LSTM) network, off-chip activation vector-vector generate inputs used next on- MAC.